Method for fabricating a trench structure, and a semiconductor arrangement comprising a trench structure

ABSTRACT

A semiconductor device, in which a first trench section is produced proceeding from a surface of a semiconductor body into the semiconductor body. A semiconductor layer is produced above the surface and above the first trench section. A further trench section is produced in the semiconductor layer in such a way that the first trench section and the further trench section form a continuous trench structure.

CROSS-REFERENCE TO RELATED APPLICATIONS

This Utility Patent Application claims priority to DE Application No. 102006 037 510.6, filed Aug. 10, 2006, which is herein incorporated byreference.

BACKGROUND

The present disclosure relates to a method for fabricating a trenchstructure, and to a semiconductor arrangement including a trenchstructure.

Trench structures, also known as trenches, principally find applicationin semiconductor technology for isolating integrated components andstorage capacitors in dynamic memories (DRAMs). However specialapplications are also known for power semiconductor components, such ase.g., for a Trench Extended Drain Region Filed-effect Transistor(TEDFET). The construction of a TEDFET is described in the publishedpatent application DE 10 2005 039 33 1.

In this case, the trend is towards ever narrower and at the same timedeeper trench structures. One important measure of this is the aspectratio, that is to say the ratio of depth to width of the trench.

Trench structures are generally produced by anisotropic etchingprocesses, in particular by dry etching processes. Trench structureshaving an aspect ratio of 80:1 can be fabricated thereby at the presenttime.

For these and other reasons there is a need for the present invention.

SUMMARY

Embodiments of the present invention provide a method for fabricating atrench structure having a high aspect ratio and a semiconductorarrangement including a deep trench structure. The method according toone embodiment of the invention includes producing a first trenchsection proceeding from a surface of a semiconductor body into thesemiconductor body, producing a semiconductor layer above the surfaceand above the first trench section, and producing a further trenchsection in the semiconductor layer in such a way that the first trenchsection and the further trench section form a continuous trenchstructure.

The step-by-step construction of the trench structure from individualtrench sections in the semiconductor arrangement makes it possible toproduce the ultimately desired trench structure with an aspect ratiothat has not been achieved heretofore by virtue of the composition ofthe individual trench sections.

The semiconductor arrangement according to exemplary embodiments of theinvention has a trench structure, wherein the trench structure iscomposed of a plurality of vertical trench sections and at least onelateral connecting element. The lateral connecting element serves tocompensate for a possibly occurring offset between vertical trenchsections arranged one above another, and to connect the offset verticaltrench sections to one another. This gives rise to a continuous trenchstructure without interruption.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide a furtherunderstanding of the present invention and are incorporated in andconstitute a part of this specification. The drawings illustrate theembodiments of the present invention and together with the descriptionserve to explain the principles of the invention. Other embodiments ofthe present invention and many of the intended advantages of the presentinvention will be readily appreciated as they become better understoodby reference to the following detailed description. The elements of thedrawings are not necessarily to scale relative to each other. Likereference numerals designate corresponding similar parts.

FIG. 1 to FIG. 5 illustrate schematic cross-sectional views ofindividual method results of an exemplary embodiment of the methodaccording to the invention.

FIG. 6 illustrates a schematic cross-sectional view of an exemplaryembodiment of the semiconductor arrangement according to the invention.

FIG. 7 illustrates a schematic detail view A from FIG. 6 in a firstembodiment of the semiconductor arrangement according to the invention.

FIG. 8 illustrates a schematic detail view A from FIG. 6 in a furtherembodiment of the semiconductor arrangement according to the invention.

FIG. 9 illustrates a schematic detail view A from FIG. 6 in a furtherembodiment of the semiconductor arrangement according to the invention.

FIG. 10 illustrates a schematic detail view A from FIG. 6 in a furtherembodiment of the semiconductor arrangement according to the invention.

FIG. 11 illustrates a schematic detail view A from FIG. 6 in a furtherembodiment of the semiconductor arrangement according to the invention.

DETAILED DESCRIPTION

In the following Detailed Description, reference is made to theaccompanying drawings, which form a part hereof, and in which is shownby way of illustration specific embodiments in which the invention maybe practiced. In this regard, directional terminology, such as “top,”“bottom,” “front,” “back,” “leading,” “trailing,” etc., is used withreference to the orientation of the Figure(s) being described. Becausecomponents of embodiments of the present invention can be positioned ina number of different orientations, the directional terminology is usedfor purposes of illustration and is in no way limiting. It is to beunderstood that other embodiments may be utilized and structural orlogical changes may be made without departing from the scope of thepresent invention. The following detailed description, therefore, is notto be taken in a limiting sense, and the scope of the present inventionis defined by the appended claims.

It is pointed out that identical elements in the figures are providedwith the same or similar reference symbols, and that a repeateddescription of the elements is omitted.

The described method for fabricating a trench structure can be used forexample for fabricating a trench structure in a TEDFET. TEDFET (TrenchExtended Drain Region Field-effect transistors) are distinguished by thefact that a deep and very thin dielectric layer is required between adrift zone and a drift control zone. The dielectric layer can befabricated by the method according to the invention.

That region of the dielectric layer which separates the drift zone andthe drift control zone is also referred to as “accumulation dielectric”.In the case of a TEDFET the terms “drift zone” or “drift path” denote asemiconductor region in which a reverse voltage is reduced uponapplication of the reverse voltage to the component, that is to say inwhich a space charge zone propagates as the reverse voltage increases.

The doping of the drift control zone is chosen such that the latter hasat least one semiconductor section which can be fully depleted in adirection perpendicular to the accumulating dielectric. This istantamount to the fact that the dopant atoms present in thesemiconductor section can be fully ionized when an electric field ispresent in a direction perpendicular to the accumulation dielectric,without an avalanche breakdown occurring. This can be achieved by virtueof the fact that a quotient of a net dopant charge in a semiconductorsection adjoining the trench structure and the drift zone and the areaof the trench structure arranged between the drift control zone and thedrift zone is less than the breakdown charge of the drift control zone,which lies within a range of approximately 1·10¹²/cm² to approximately2·10¹²/cm².

When the component is driven in the on state, the drift control zoneserves for controlling an accumulation channel, i.e. a region havinglocally greatly increased charge carrier density, in the drift zonealong the accumulation dielectric. A potential difference between thedrift control zone and the drift zone is required for forming thechannel. In this case, the type of charge carriers, that is to sayelectrons or holes, which accumulate along the accumulation dielectricis dependent on the polarity of the potential difference, but not on thebasic doping of the drift zone, which can also be realized as an undopedor intrinsic zone.

The presence of such an accumulation channel leads to a considerablereduction of the on resistance of the power semiconductor component incomparison with components which do not have such a drift control zone.For the same on resistance, it is possible to reduce the basic doping ofthe drift zone of the TEDFET in comparison with the basic doping of thedrift zone of conventional components, which results in a higherdielectric strength of the TEDFET in comparison with conventionalcomponents.

The drift zone is capacitively coupled to the drift control zone via theaccumulation dielectric, whereby the accumulation channel can be formedwhen the component is driven in the on state. This capacitive couplingand the compliance with the above-specified doping condition for thedrift control zone have the effect that in the case of components in theoff state, that is to say when a space charge zone propagates in thedrift zone, a space charge zone likewise propagates in the drift controlzone. This space charge zone propagating in the drift control zone hasthe effect that the potential profile in the drift control zone followsthe potential profile in the drift zone. A potential difference or anelectrical voltage between the drift zone and the drift control zone isthereby limited. This voltage limiting makes it possible to use a thinaccumulation dielectric, which entails the advantage of an improvedcapacitive coupling between the drift control zone and the drift zone.

In this case, the desired width of the trench structure and therefore ofeach individual trench section is proportioned to the static voltagedifference between drift zone and drift control zone that is presentduring operation of the TEDFET.

FIG. 1 illustrates a first intermediate state of the method of a firstexemplary embodiment of the invention.

In this first exemplary embodiment of the method according to theinvention for fabricating a trench structure, a first process involvesproducing a first trench section 2 from a surface 3 of a semiconductorbody 1 into the semiconductor body.

For this purpose, firstly a mask layer (e.g., a hard mask—notillustrated in FIG. 1) is applied on the surface 3 of the semiconductorbody and patterned. Afterwards, the first trench section 2 is etched(trench etch) and passivated with an oxide layer 10 on the sidewalls.This is done with the aid of the spacer technique, in which firstly theentire surface is coated with an oxide layer 10 and the oxide layer 10is subsequently removed again on the surface 3 and at the bottom of thetrench by using an anisotropic etch, such that the oxide layer 10remains only on the side walls of the trench section 2. Instead of theoxide, it is also possible, in principle, to use other insulator layerssuch as Si₃N₄ or layer stacks of a plurality of insulator materials. Incontrast to the illustration in FIG. 1, the trench can also becompletely filled with a dielectric which is homogeneous or constructedin layered fashion and which can remain in the trench.

The first trench section 2 is produced with an approximately uniformwidth B within the range of 30-150 nm. The depth T of the trench section2 results from the width B chosen and the available etching technology.Given an at the present time maximum possible aspect ratio ofapproximately 80:1, therefore, the maximum achievable depth of thetrench section 2 is 12 μm if the width B is chosen at 150 nm. A depth Tof approximately 1-6 μm is normally striven for.

The alignment of the first trench section 2 is achieved by usingspecifically dimensioned alignment structures in a semiconductor regionnot required for the electrical function of the semiconductorcomponent—e.g., in a scribing frame (not illustrated in FIG. 1). Whilethe trenches are intended to be overgrown during the subsequentdeposition of the next semiconductor layer as far as possible withoutconspicuous features such as e.g., processes or depressions, it is inthe nature of the alignment structures that they must still beidentified after the deposition process, which can be realized e.g., byusing a trench structure that is at least as wide as the width B of thetrenches in the active semiconductor region. As an alternative, thealignment structures can also be applied on or introduced into the rearside of the semiconductor wafer, whereby they are protected againstdepositions on the front side of the wafer.

FIG. 2 illustrates a semiconductor layer 4 that was produced above thesurface 3 and above the first trench section 2.

The semiconductor layer 4 is produced epitaxially and with a highdeposition rate. By using this non-conformable process, the trenchsection 2 is completely buried, that is to say that semiconductor layer4 grows over the trench section 2 and bridges the latter.

The semiconductor layer 4 grows in monocrystalline fashion from the samesemiconductor material as the semiconductor body 1 and, in view of thetrench dimensioning, becomes thinner than the maximum achievable trenchdepth, that is to say is normally deposited up to a thickness ofapproximately 1-6 μm.

FIG. 3 illustrates a further trench section 2 in the semiconductor layer4. The further trench section 2 in the semiconductor layer 4 wasproduced in such a way that the first trench section 2 and the furthertrench section 2 form a continuous trench structure 20.

The further trench section 2 in the semiconductor layer 4 is likewiseproduced by using a trench etch with the aid of a mask produced on thesurface of the semiconductor layer 4. The further trench section 2produced is likewise passivated with an oxide layer 10 on the side wallswith the aid of the spacer technique. The oxide layer 10 is produced bythermal oxidation. As a result, the thicknesses of oxide layers alreadypresent in other trench sections increase to a lesser extent. Thedimensioning of the further trench section 2 is oriented towards thedimensioning of the first trench section 2.

In this first exemplary embodiment of the invention, the further trenchsection 2 should be positioned as precisely as possible above the firsttrench section 2. The alignment of the further trench section 2 islikewise effected by using the specifically dimensioned alignmentstructures in the scribing frame. A misalignment of the two trenchsections 2 with respect to one another will result, however, underproductive conditions.

The following arises as a condition for a maximum permitted misalignmentin the first exemplary embodiment of the invention:

misalignment<trench section width in the underlying plane.

Trench sections 2 lying one above another should therefore at leastpartly overlap. Thus, e.g., given a trench section width B ofapproximately 100 nm, a misalignment of approximately 50 nm would stillbe tolerable.

FIG. 4 illustrates further semiconductor layers 4 with further trenchsections 2, which are formed by repeating the processes

producing a semiconductor layer 4 above the surface 3 and above thefirst trench section 2, and

producing a further trench section 2 in the semiconductor layer 4 insuch a way that the first trench section 2 and the further trenchsection 2 form a continuous trench structure 20,

until the trench structure 20 has reached a desired depth T′.

The depth T′ of the trench structure is formed with at least 10 μm. Thesame conditions as explained in the method processes concerning FIG. 2and FIG. 3 hold true for the method implementation of these furtherprocesses.

As illustrated in FIG. 5, for the ultimately desired trench structure 20in this first exemplary embodiment of the invention, the oxide layers 10are stripped from the sidewalls of the trench sections 2 and processesthus possibly formed between two trench sections 2 are smoothed by usinga H₂ heat treatment. In this case, H₂ gas is introduced into the trenchstructure 20 at a temperature within the range of 800-900° C. and with aheat treatment time within the range of 2-15 minutes.

Afterwards, the trench structure 20 is at least partly filled with afilling material. Depending on the application, dielectric, inparticular high-k material, is at least partly used as filling material.High-k materials are dielectrics having a higher relative permittivity∈_(r) than conventional SiO₂ (∈_(r)=3.9) or oxynitrides (∈_(r)<6) orSi₃N₄ (∈_(r)≈6.9). A combination of thermally produced SiO₂ directly onthe semiconductor surface followed by a further dielectric layer, e.g.,a high-k material, is.

The above-described etching out of lateral dielectric layers, thesmoothing of processes and the filling with a new homogeneous or layereddielectric are optional process processes.

FIG. 6 illustrates an exemplary embodiment of the semiconductorarrangement according to the invention.

An epitaxial layer is arranged on an n⁺-type substrate, the epitaxiallayer together with the n⁺-type substrate forming a semiconductor body1. A plurality of vertical trench sections 2 are arranged in thesemiconductor body, the trench sections being spaced apart laterallyfrom one another and extending into the semiconductor body 1.

A plurality of semiconductor layers 4 lying one above another arearranged on the semiconductor body 1, a plurality of vertical trenchsections 2 in turn being arranged in each semiconductor layer 4.

The semiconductor layers 4 are layers grown epitaxially, for example.The vertical trench sections 2 extend in each case through therespective semiconductor layer 4. Lateral connecting elements 5 arearranged between in each case two semiconductor layers 4 lying one ontop of another, and between the first semiconductor layer 4 and thesemiconductor body 1, the connecting elements connecting in each casetwo closest vertical trench sections 2 from different semiconductorlayers. The closest trench sections 2 from different semiconductorlayers are slightly offset laterally in this case. The offset or an onlypartial overlap can stem e.g., from a misalignment of the planes withrespect to one another. The connecting elements 5 bridge the offset.Consequently, the trench structure 20 formed in this way extends incontinuous form through all the semiconductor layers 4 right into thesemiconductor body 1 as a narrow and deep trench structure 20. Thetrench structure 20 is therefore composed of a plurality of verticaltrench sections 2 and at least one lateral connecting element 5, whereinthe vertical trench sections 2 and the at least one lateral connectingelement 5 are formed identically in type. However, applications can alsooccur in which the vertical trench sections 2 and the at least onelateral connecting element are formed differently.

The illustrated semiconductor arrangement 15 of the exemplary embodimentis part of TEDFET having a drift zone 6 and a drift control zone 7,which are separated from one another by a narrow dielectric layer. Inthe exemplary embodiment illustrated, the dielectric layer is formed bythe trench structure 20 filled with a dielectric. The drift control zone7 has, at the junction of the n⁺-type substrate used as drain terminal,that is to say here at the end of the trench structure 20, an oppositedoping to the semiconductor body 1 and semiconductor layer 4. It is ap⁺-type zone in the exemplary embodiment illustrated.

FIG. 6 illustrates only part of the TEDFET, but not the cell structurewith source, body and gate. In particular planar and also trench MOScells are suitable for the cell structure.

The trench structure in the semiconductor arrangement as illustrated inFIG. 6 can be fabricated by the fabrication method according to theinvention as explained by way of example in FIGS. 1 to 5. Lateral layersare produced between the individual epitaxy processes for thefabrication of the semiconductor layers 4, the layers in each case beingpatterned in such a way that connecting elements 5 are formed, whichconnect two laterally spaced-apart trench sections 2 laying one overanother to one another.

In the exemplary embodiment of FIG. 6, the connecting elements 5 areformed from a dielectric layer, and in terms of the thickness andcomposition are for example identical to the final thickness andcomposition of the dielectric in the entire trench structure 20.

After the patterning of the lateral connecting element 5, a newsemiconductor layer 4 is deposited epitaxially, a selective growth beingchosen at the beginning of the deposition in order that the lateraldielectric layers are epitaxially overgrown laterally. Faster depositionconditions can subsequently be chosen.

A suitable dielectric is SiO₂ or else, in particular, layer stacksincluding SiO₂ and Si₃N₄ and oxynitrides, in order to minimizethermomechanical stress with respect to the silicon semiconductormaterial of the semiconductor body 1 and with respect to thesemiconductor layers 4. Dielectrics having medium and/or high k valuesare likewise suitable.

FIG. 7 illustrates a detail excerpt A from FIG. 6. A drift zone 6 withthe adjacent drift zone 7 of a TEDFET is illustrated at the junctionbetween two successive epitaxial semiconductor layers 4. The drift zone6 and the drift control zone 7 are separated from one another by adielectric layer. The dielectric layer is formed by the vertical trenchsections 2 filled with dielectric and the lateral connecting elements 5composed of the same dielectric. The desired accumulation of chargecarriers in the drift zone 6 and the drift control zone 7 duringoperation of a TEDFET takes place not only along the vertical trenchsections 2 but also along the lateral connecting elements 5. As aresult, an increase in the on resistance remains limited even as aresult of the stepped course of the dielectric.

FIG. 8 illustrates the detail excerpt A in a further embodiment of theTEDFET, an additional n-type doping 9 being implanted into the top sideof the lower n-doped semiconductor layer 4. By using subsequent thermalprocesses, the dopant is also out diffused into the adjacent n-dopedsemiconductor layer 4. The additional n-type doping reduces theadditional current resistance component specifically at the ends of thelateral connecting element 5, at which, due to the dictates of geometry,there is the greatest level of distance with respect to the controllingcharge of the drift control zone 7.

FIG. 9 illustrates a further embodiment of the TEDFET, in which thesemiconductor layers 4 are fabricated as p-doped layers. At the junctionbetween two semiconductor layers 4, once again by using an n-type dopantimplantation with subsequent out diffusion, an n-type doping 9 is formedat the ends of the lateral connecting element 5 for the purpose ofreducing the current resistance component.

The p-type doping of the semiconductor layers 4 leads, in the drift zone6, to an electron inversion channel without any significant influence onthe on resistance.

FIG. 10 illustrates a further embodiment of the TEDFET, which involvesthe introduction of an additional n-type doping 9 in p-type doping ofthe semiconductor layer 4 only in the region of the drift zone 6. As aresult, a breakdown of the component occurs firstly in the drift zone 6.The drift control zone 7 therefore has a higher blocking capability,which has a favourable effect on the avalanche behaviour.

The lateral extent of the additional n-type doping 9 can be varied inthis case, such that, by way of example, the doping reaches as far asthe closest vertical trench section 2. Particularly if the n-type doping9 is introduced before the formation of the lateral connecting element 5e.g., by ion implantation of phosphorus, the closet vertical trenchsection 2 constitutes a barrier, such that the diffusion is braked there(not illustrated in FIG. 10-cf. FIG. 11).

FIG. 11 illustrates a further embodiment of a TEDFET, in which an n-typedoping 9 is introduced only locally into the drift zone 6 of a p-dopedsemiconductor layer 4. By way of example, the n-type doping 9 reacheslaterally as far as the closest vertical trench section 2. This localintroduction of n-type doping 9 into the drift zone 6 enables areduction of the net p-type doping in the adjoining drift control zone7.

All the above-mentioned exemplary embodiments and embodiments are notintended to be understood as final examples for the method according tothe invention and the semiconductor arrangement according to theinvention, but rather are intended merely to elucidate the invention byway of example.

Although specific embodiments have been illustrated and describedherein, it will be appreciated by those of ordinary skill in the artthat a variety of alternate and/or equivalent implementations may besubstituted for the specific embodiments illustrated and describedwithout departing from the scope of the present invention. Thisapplication is intended to cover any adaptations or variations of thespecific embodiments discussed herein. Therefore, it is intended thatthis invention be limited only by the claims and the equivalentsthereof.

1. A method for fabricating a semiconductor device comprising: a)producing a first trench section proceeding from a surface of asemiconductor body into the semiconductor body; b) producing asemiconductor layer above the surface and above the first trenchsection; and c) producing a further trench section in the semiconductorlayer in such a way that the first trench section and the further trenchsection form a continuous trench structure.
 2. The method of claim 1,comprising: d) repeating steps b) and c) until the trench structure hasreached a desired depth T′.
 3. The method of claim 1, wherein thesemiconductor layer is produced epitaxially.
 4. The method of claim 1,wherein the semiconductor layer is produced with a thickness of between1 μm and 12 μm, in particular between 1 μm and 6 μm.
 5. The method ofclaim 1, wherein the trench structure is formed with a depth T′ of atleast 10 μm.
 6. The method of claim 1, wherein the semiconductor layeris produced from the same semiconductor material as the semiconductorbody.
 7. The method of claim 1, wherein the semiconductor layer is dopedduring or after production.
 8. The method of claim 7, wherein the dopingis varied in a lateral and/or vertical direction.
 9. The method of claim1, wherein each trench section is produced with a uniform width B. 10.The method of claim 1, wherein the trench sections are in each caseproduced by an etch.
 11. The method of claim 1, wherein each trenchsection is at least partly filled with filling material.
 12. The methodof claim 11, wherein a dielectric is at least partly used as fillingmaterial.
 13. The method of claim 12, wherein a high-k material is atleast partly used as dielectric.
 14. The method of claim 1, whereintrench sections lying one above another at least partly overlap.
 15. Themethod of claim 1, wherein, before producing the semiconductor layer, alayer is produced parallel to the surface of the semiconductor body andpatterned in such a way that a connecting element is formed, whichconnects two trench sections lying one above another to one another. 16.The method of claim 1, wherein, before producing the semiconductorlayer, a layer is produced parallel to the surface of the semiconductorbody and patterned in such a way that a connecting element is formed,which connects two laterally spaced-apart trench sections lying oneabove another to one another.
 17. The method of claim 15, wherein thelayer is produced with a thickness equal to the width of the trenchsections.
 18. The method of claim 15, wherein the connecting element isconfigured like the trench sections to be connected.
 19. The method ofclaim 15, wherein the semiconductor layer is produced by selectivegrowth at least at the beginning of production.
 20. The method of claim1, wherein the semiconductor device is a TEDFET.
 21. A semiconductorarrangement comprising: a trench structure, wherein the trench structureis composed of a plurality of vertical trench sections, and at least onelateral connecting element.
 22. The semiconductor arrangement of claim21, wherein the semiconductor arrangement has a plurality ofsemiconductor layers lying one above another.
 23. The semiconductorarrangement of claim 22, wherein the semiconductor layers are epitaxiallayers.
 24. The semiconductor arrangement of claim 21, wherein a firstvertical trench section is arranged in a first semiconductor layer and asecond vertical trench section is arranged in a second semiconductorlayer arranged above the first semiconductor layer.
 25. Thesemiconductor arrangement of claim 24, wherein the connecting element isarranged between the first and the second semiconductor layer.
 26. Thesemiconductor arrangement of claim 21, wherein the trench sections andthe at least one connecting element are configured identically in kind.27. The semiconductor arrangement of claim 21, wherein the trenchstructure is filled.
 28. The semiconductor arrangement of claim 27,wherein the trench structure is at least partly filled with adielectric.
 29. The semiconductor arrangement of claim 21, wherein thesemiconductor arrangement forms a TEDFET.
 30. The semiconductorarrangement of claim 29, wherein the trench structure separates a driftcontrol zone in the semiconductor arrangement from a drift zone in thesemiconductor arrangement.
 31. The semiconductor arrangement of claim30, wherein a quotient of a net dopant charge of the drift control zonein a semiconductor section adjoining the trench structure and the driftzone and the area of the trench structure arranged between the driftcontrol zone and the drift zone is less than the breakdown charge of thedrift control zone.